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ISL84780
Data Sheet October 11, 2004 FN6099.0
Ultra Low ON-Resistance, Low Voltage, Single Supply, Quad 2:1 Analog Multiplexer
The Intersil ISL84780 device is a low ON-resistance, low voltage, bidirectional, Quad SPDT (Dual DPDT) analog switch designed to operate from a single +1.6V to +3.6V supply. Targeted applications include battery-powered equipment that benefit from low on-resistance, and fast switching speeds (tON = 12ns, tOFF = 8ns). The digital logic input is 1.8V logic-compatible when using a single +3V supply. Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This family of parts may be used to "mux-in" additional functionality while reducing ASIC design risk. The ISL84780 is offered in small form factor packages, alleviating board space limitations. The ISL84780 is a committed Quad SPDT that consists of four normally open (NO) and four normally closed (NC) switches. This configuration can also be used as a diff dual 2to-1 multiplexer/demultiplexer or a quad 2-to1 multiplexer/demultiplexer. The ISL84780 is pin compatible with the MAX4780.
TABLE 1. FEATURES AT A GLANCE ISL84780 Number of Switches SW 3.0V RON 3.0V tON/tOFF 1.8V RON 1.8V tON/tOFF Packages 4 Quad SPDT (Dual DPDT) 0.36 12ns/8ns 0.54 19ns/11ns 16Ld 3x3 TQFN, 16Ld TSSOP
Features
* Pin Compatible Replacement for the MAX4780 * ON Resistance (RON) - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.36 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.54 * RON Matching between Channels. . . . . . . . . . . . . . . . . 0.13 * RON Flatness Across Signal Range . . . . . . . . . . . . . . . 0.05 * Single Supply Operation . . . . . . . . . . . . . . . . .+1.6V to +3.6V * Low Power Consumption (PD) . . . . . . . . . . . . . . . . . <0.2W * Fast Switching Action - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns * Guaranteed Break-Before-Make * 1.8V Logic Compatible (+3V supply) * Available in 16 lead 3x3 thin QFN and 16 lead TSSOP * ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
Applications
* Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Portable Test and Measurement * Medical Equipment * Audio and Video Switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL84780 Pinouts
(Note 1) ISL84780 (TSSOP) TOP VIEW
IN1-2 NC1 NO1 COM1 NC2 NO2 COM2 GND 1 2 3 4 5 6 7 8 16 V+ 15 IN3-4 14 NC4 13 NO4 12 COM4 11 NC3 10 NO3 9 COM3
Ordering Information
PART NO. (BRAND) ISL84780IR (780I) ISL84780IR-T (780I) ISL84780IV (84780IV) ISL84780IV-T (84780IV) TEMP. RANGE (C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 16 Ld 3x3 Thin QFN 16 Ld 3x3 Thin QFN Tape and Reel 16 Ld TSSOP 16 Ld TSSOP Tape and Reel PKG. DWG. # L16.3x3A L16.3x3A M16.173 M16.173
Truth Table
ISL84780 (3X3 THIN QFN) TOP VIEW
IN1-2 IN3-4 NC1 V+
LOGIC 0 1 NOTE:
NC SW ON OFF
NO SW OFF ON
Logic "0" 0.5V. Logic "1" 1.4V with a 3V supply.
16 NO1 COM1 NC2 NO2 1 2 3 4 5 COM2
15
14
13 12 11 10 9 NC4 NO4 COM4 NC3
Pin Descriptions
PIN V+ GND IN COM NO FUNCTION System Power Supply Input (+1.6V to +3.6V) Ground Connection Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin
6 GND
7 COM3
8 NO3
NOTE: 1. Switches Shown for Logic "0" Input.
NC
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ISL84780
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V Input Voltages NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA ESD Rating: HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 16 Ld 3x3 TQFN Package . . . . . . . . . . . . . . . . . . . . 75 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Junction Temperature (Plastic Package). . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6), Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at max RON, (Note 9) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+ (Note 7) V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 Full 25 Full 25 Full 25 Full V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V, or Floating 25 Full
0 -3 -20 -4 -30
0.4 0.13 0.05 -
V+ 0.6 0.7 0.2 0.2 0.15 0.15 3 20 4 30
V nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 8) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 8) V+ = 3.3V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 3, Note 8) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 4) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 6) f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32
25 Full 25 Full Full 25 25 25 25 25 25
1 -
12 8 3 -97 68 -98 0.002 62 125
20 25 14 17 -
ns ns ns ns ns pC dB dB % pF pF
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
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ISL84780
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+
Full V+ = 3.6V, VIN = 0V or V+ 25 Full
1.6 -
-
3.6 0.05 1.5
V A A
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL NOTES: 4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parts are 100% tested at +25C. Limits across the full temperature range are guaranteed by design and correlation. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Guaranteed not tested. 9. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4. V+ = 3.6V, VIN = 0V or V+ (Note 8) Full Full Full 1.4 -0.5 0.5 0.5 V V A
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 4, 6), Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+, See Figure 5 25 Full
0 -
0.54 -
V+ 0.9 1
V
DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 1.65V, VNO or VNC = 1.0V, RL =50, CL = 35pF, See Figure 1, Note 8 V+ = 1.65V, VNO or VNC = 1.0V, RL =50, CL = 35pF, See Figure 1, Note 8 V+ = 2.0V, VNO or VNC = 1.0V, RL =50, CL = 35pF, See Figure 3, Note 8 CL = 1.0nF, VG = 0V, RG = 0, See Figure 2 RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, See Figure 4 RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, See Figure 6 25 Full 25 Full Full 25 25 25 25 25 1 19 11 5 -52 68 -98 62 125 25 30 17 22 ns ns ns ns ns pC dB dB pF pF
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel)
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ (Note 8) Full Full Full 1.0 -0.05 0.4 0.05 V V A
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ISL84780 Test Circuits and Waveforms
V+ VINH LOGIC INPUT 50% VINL tOFF SWITCH INPUT VNO 90% SWITCH OUTPUT 0V tON VOUT 90% SWITCH INPUT tr < 5ns tf < 5ns NO or NC COM IN LOGIC INPUT GND RL 50 CL 35pF VOUT C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R L + R ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
V+
C
SWITCH OUTPUT VOUT
VOUT
RG
NO or NC
COM
VOUT
VINH LOGIC INPUT ON OFF VINL Q = VOUT x CL ON
VG
GND
IN
CL LOGIC INPUT
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V+
C
VINH LOGIC INPUT VINL VNX
NO
COM
NC
VOUT RL 50 CL 35pF
IN SWITCH OUTPUT VOUT 90% 0V tD LOGIC INPUT GND
CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME FIGURE 3B. TEST CIRCUIT
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ISL84780 Test Circuits and Waveforms (Continued)
V+ C SIGNAL GENERATOR RON = V1/1mA
NO or NC NO or NC
V+ C
VNX IN 0V or V+ 1mA V1 IN VINL or VINH
ANALYZER RL
COM
COM
GND
GND
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. RON TEST CIRCUIT
V+ C V+ C SIGNAL GENERATOR
NO or NC COM
50
NO or NC
IN1 0V or V+ IMPEDANCE ANALYZER
COM NC or NO COM
IN
VINL or VINH
ANALYZER RL
N.C.
GND
GND
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL84780 is a bidirectional, quad single pole/double throw (SPDT) analog switch that offers precise switching capability from a single 1.6V to 3.6V supply with low onresistance (0.36) and high speed operation (tON = 12ns, tOFF = 8ns). The device is especially well suited for portable battery-powered equipment due to its low operating supply voltage (1.6V), low power consumption (5.4W max), low leakage currents (30nA max), and the tiny TQFN and TSSOP packages. The ultra low on-resistance and Ron flatness provide very low insertion loss and distortion to applications that require signal reproduction. voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (See Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (See Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal
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ISL84780
High-Frequency Performance
OPTIONAL PROTECTION DIODE V+ OPTIONAL PROTECTION RESISTOR INX VNO or NC VCOM
In 50 systems, the signal response is reasonably flat even past 30MHz with a -3dB bandwidth of 104MHz (See Figure 15). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from the switch input to its output. Off Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 16 details the high Off Isolation and Crosstalk rejection provided by this part. At 100kHz, Off Isolation is about 68dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
GND OPTIONAL PROTECTION DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL84780 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL84780 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.6V but the part will operate with a supply below 1.5V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.0V to 3.6V (See Figure 17). At 3.6V the VIH level is about 1.27V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
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ISL84780 Typical Performance Curves TA = 25C, Unless Otherwise Specified
0.55 ICOM = 100mA 0.5 V+ = 1.8V 0.35 RON () RON () 0.45 25C 85C 0.4
0.4
0.3 0.35 V+ = 2.7V V+ = 3V 0.3 V+ = 3.6V 0 1 2 VCOM (V) 3 4 0.25 0 0.5 1 1.5 VCOM (V) 2 -40C V+ = 3V ICOM = 100mA 2.5 3
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
0.6 85C 0.55 25C 0.5 -40C RON () 0.45
100 V+ = 1.8V ICOM = 100mA 50 V+ = 3V 0 Q (pC) V+ = 1.8V -50
0.4 -100
0.35
0.3
-150 0 0.5 1 VCOM (V) 1.5 2 0 0.5 1 1.5 VCOM (V) 2 2.5 3
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
50
20
40
15
tOFF (ns)
tON (ns)
30 85C 25C
10
85C
25C
20
-40C 5
10
-40C
0
0 1 1.5 2 2.5 3 V+ (V) 3.5 4 4.5
1
1.5
2
2.5 V+ (V)
3
3.5
4
4.5
FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE
FN6099.0
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ISL84780 Typical Performance Curves TA = 25C, Unless Otherwise Specified (Continued)
NORMALIZED GAIN (dB) -10 V+ = 3V 0 -20 CROSSTALK (dB) GAIN V+ = 3V -20 -30 -40 -50 -60 ISOLATION -70 -80 -90 -100 -110 1k 10k 100k 1M 10M FREQUENCY (Hz) CROSSTALK 70 80 90 100 110 100M 500M 20 30 40 50 60 OFF ISOLATION (dB) 10
20 40 60 80 RL = 50 VIN = 0.2VP-P to 2VP-P 1 10 100 FREQUENCY (MHz) 100 600
FIGURE 15. FREQUENCY RESPONSE
1.5 1.4 1.3 1.2 VINH AND VINL (V) 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 1 1.5 2 2.5 V+ (V) 3 3.5 4 4.5 VINL VINH
PHASE (DEGREES)
PHASE
0
FIGURE 16. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND (QFN Paddle Connection: To Ground or Float) TRANSISTOR COUNT: 228 PROCESS: Si Gate CMOS
FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
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ISL84780 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.033 0.0075 0.0035 0.193 0.169 MAX 0.043 0.006 0.037 0.012 0.008 0.201 0.177 MILLIMETERS MIN 0.05 0.85 0.19 0.09 4.90 4.30 MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 NOTES 9 3 4 6 7 8o Rev. 1 2/02
A1 0.10(0.004) A2 c
E1 e E L N
e
b 0.10(0.004) M C AM BS
0.026 BSC 0.246 0.020 16 0o 8o 0.256 0.028
0.65 BSC 6.25 0.50 16 0o 6.50 0.70
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
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ISL84780 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP)
)
2X A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 4X 0 TOP VIEW A2 B E/2 E 2X 0.15 C B D D/2 0.15 C A
L16.3x3A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L N Nd Ne P 1.35 0.20 0.30 1.35 0.18 MIN 0.70 NOMINAL 0.75 0.20 REF 0.23 3.00 BSC 2.75 BSC 1.50 3.00 BSC 2.75 BSC 1.50 0.50 BSC 0.40 16 4 4 0.60 12 0.50 1.65 1.65 0.30 MAX 0.80 0.05 0.80 NOTES 9 9 5, 8 9 7, 8, 10 9 7, 8, 10 8 2 3 3 9 9 Rev. 0 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
A
/ / 0.10 C 0.08 C
C A1
SEATING PLANE
SIDE VIEW NX b 5
A3
9
4X P D2 (DATUM B) 4X P D2 2N
0.10 M C A B 7 8 NX k
1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF.
9 CORNER OPTION 4X
SECTION "C-C" C L C L
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
L1 e 10 L
L1 CC e
10
L
9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2 and D2 MAX dimension.
TERMINAL TIP FOR EVEN TERMINAL/SIDE
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
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